EL4583 Fn7173.2 Data Sheet

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Elantec - Intersil EL4583
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  1  ®  FN7173.2  EL4583  Sync Separator, 50% Slice, S-H, Filter,H  OUT  The EL4583 extracts timing from video sync in NTSC, PAL,and SECAM systems, and non standard formats, or fromcomputer graphics operating at higher scan rates. Timingadjustment is via an external resistor. Input without validvertical interval (no serration pulses) produces a defaultvertical output.Outputs are: composite sync, vertical sync, filter, burst/backporch, horizontal, no signal detect, level, and odd/evenoutput (in interlaced scan formats only).The EL4583 sync slice level is set to the mid-point betweensync tip and the blanking level. This 50% point is determinedby two internal sample and hold circuits that track sync tipand back porch levels. It provides hum and noise rejectionand compensates for input levels of 0.5V to 2.0V P-P .A built in filter attenuates the chroma signal to prevent colorburst from disturbing the 50% sync slice. Cut off frequency isset by a resistor to ground from the Filter Cut Off pin.Additionally, the filter can be by-passed and video signal feddirectly to the Video Input.The level output pin provides a signal with twice the syncamplitude which may be used to control an external AGCfunction. A TTL/CMOS compatible No Signal Detect Outputflags a loss or reduction in input signal level. A resistor setsthe Set Detect Level.The EL4583 is manufactured using Intersil’s highperformance analog CMOS process. Features  ãNTSC, PAL, and SECAM sync separationãSingle supply, +5V operationãPrecision 50% slicingãBuilt-in programmable color burst filterãDecodes non-standard verticalãHorizontal sync outputãSync. pulse amplitude outputãSame socket can be used for 8 Ld EL4581ãLow-power CMOSãDetects loss of signalãResistor programmable scan rateãFew external componentsãAvailable in 16 Ld PDIP and 16 Ld SO (0.150”) packagesãPb-free plus anneal available (RoHS compliant) Applications  ãVideo special effectsãVideo test equipmentãVideo distributionãMultimediaãDisplaysãImagingãVideo data captureãVideo triggers Pinout Ordering Information  PART NUMBERPARTMARKINGTAPE &REELPACKAGEPKG.DWG. # EL4583CNEL4583CN-16 Ld PDIPMDP0031EL4583CSEL4583CS-16 Ld SO (0.150”)MDP0027EL4583CS-T7EL4583CS7”16 Ld SO (0.150”)MDP0027EL4583CS-T13EL4583CS13”16 Ld SO (0.150”)MDP0027EL4583CSZ(Note)EL4583CSZ-16 Ld SO (0.150”)(Pb-free)MDP0027EL4583CSZ-T7(Note)EL4583CSZ7”16 Ld SO (0.150”)(Pb-free)MDP0027EL4583CSZ-T13(Note)EL4583CSZ13”16 Ld SO (0.150”)(Pb-free)MDP0027NOTE:Intersil Pb-free plus anneal products employ special Pb-freematerial sets; molding compounds/die attach materials and 100%matte tin plate termination finish, which are RoHS compliant andcompatible with both SnPb and Pb-free soldering operations. IntersilPb-free products are MSL classified at Pb-free peak reflowtemperatures that meet or exceed the Pb-free requirements ofIPC/JEDEC J STD-020. 12341615141356712111089FILTER CUT OFFSET DETECT LEVELCOMPOSITE SYNC OUTFILTER INPUTVERTICAL SYNC OUTDIGITAL GNDFILTER OUTPUTCOMPOSITE VIDEO INPUT ANALOG GNDHORIZONTAL SYNC OUTVDDODD/EVEN OUTPUTRSET*BURST/BACK PORCH OUTPUTNO SIGNAL DETECT OUTPUTLEVEL OUTPUT EL4583(16 LD SO, PDIP) TOP VIEW *NOTE: R SET must be a 1% register Data SheetMay 5, 2006  CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.Copyright Intersil Americas Inc. 2002, 2003, 2005, 2006. All Rights ReservedAll other trademarks mentioned are the property of their respective owners.  2  FN7173.2May 5, 2006 Absolute Maximum Ratings (T A = 25°C)V CC Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7VStorage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°CPin Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V CC +0.5VOperating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°CPower Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See CurvesDie Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .150°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.IMPORTANT NOTE:All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T  J  = T  C  = T  A DC Electrical Specifications V DD = 5V, T A = 25°C, R SET = 681k Ω , R F = 22k Ω , R LV = 82k Ω PARAMETERDESCRIPTIONMINTYPMAXUNIT I DD V DD = 5V (Note 1)2.54mAClamp VoltagePins 4, 8, unloaded1.31.551.8VDischarge CurrentPins 4, 8, with signal (V IN = 2V)3612µADischarge CurrentPins 4, 8, no signal (Note 2)10µAClamp Charge CurrentPins 4, 8, V IN = 1V234mARef. Voltage V REF Pin 12, V DD = 5V (Note 3)1.51.752VFilter Reference Voltage, VRFPin 10.350.50.65VLevel Reference CurrentPin 2 (Note 4)1.52.53.5µAV OL Output Low VoltageI OL = 1.6mA350800mVV OH Output High VoltageI OH = -40µA4VI OH = -1.6mA2.44VNOTES:1.No video signal, outputs unloaded.2.At loss of signal (pin 10 high) the pull down current source switches to a value of 10µA.3.Tested for V DD 5V ±5%.4.Current sourced from pin 2 is V REF  /R SET . Dynamic Specifications R F = 22k Ω , R SET = 681k Ω , V DD = 5V, Video Input = 1V P-P , T A = 25°C, C L = 15pF, I OH = -1.6mA, I OL =1.6mA PARAMETERDESCRIPTIONMINTYPMAXUNIT Horizontal Pulse Width, Pin 15, t H (Note 1)3.856.2µsVertical Sync Width, Pin 5, t VS (Note 2)195µsBurst/Back Porch Width, Pin 11, t B (Note 1)2.73.74.7µsFilter AttenuationF IN = 3.6MHz (Note 3)12dBComp. Sync Prop. Delay, t CS V IN (Pin 4) - comp sync250400nsInput Dynamic Rangep-p NTSC signal0.42VSlice LevelInput voltage = 1V P-P 405060%V SLICE  /V BLANK 405060Level Out, Pin 9Input voltage = 1V P-P, pin 4500600700mVVertical Sync Default Time, t VSD (Note 4)273657µsLoss of Signal Time-OutPin 10400600800µsBurst/Back Porch Delay, t BD (See Figure 4)250400nsNOTES:1.Width is a function of R SET .2.C/S, vertical, back porch and H are all active low, V OH = 0.8V; vertical is 3H lines wide of NTSC signal.3.Attenuation is a function of R F . See filter typical characteristics.4.Vertical pulse width in absence of serrations on input signal. EL4583   3  FN7173.2May 5, 2006 Pin Descriptions  PINNUMBERPIN NAMEPIN FUNCTION 1Filter Cut-OffA resistor R F connected between this input and ground determines the input filter characteristic. Increasing R F  increases the filter 3.58MHz color burst attenuation. See the typical performance characteristics.2Set DetectLevelA resistor R LV connected between pin 2 and ground determines the value of the minimum signal which triggers theloss of signal output on pin 10. The relationship is V P MIN = 0.75RLV/R SET , where V P MIN is the minimum detectedsync pulse amplitude applied to pin 4. See the typical performance characteristics.3CompositeSync OutputThis output replicates all the sync inputs on the input video.4Filter InputThe filter is a 3 pole active filter with a gain of 2, designed to produce a constant phase delay of nominally 260ns withsignal amplitude. Resistor RF on pin 1 controls the filter cut-off. An internal clamp sets the minimum voltage on pin4 at 1.55V when the input becomes low impedance. Above the clamp voltage, an input current of 1µA charges theinput coupling capacitor. With loss of signal, the current source switches to a value of 10µA, for faster signal recovery.5Vertical SyncOutputThe vertical sync output is synchronous with the first serration pulse rising edge in the vertical interval of the inputsignal and ends on the trailing edge of the first equalizing Output pulse after the vertical interval. It will therefore beslightly more than 3H lines wide.6DigitalGroundThis is the ground return for digital buffer outputs.7Filter OutputOutput of the active 3 pole filter which has its input on pin 4. It is recommended to ac couple the output to pin 8.8Video InputThis input can be directly driven by the signal if it is desired to bypass the filter, for example, in the case of strongclean signals. This input is 6dB less sensitive than the filter input.9Level OutputThis pin provides an analog voltage which is nominally equal to twice the sync pulse amplitude of the video inputsignal applied to pin 4. It therefore provides an indication of signal strength.10No SignalDetectOutputThis is a digital output which goes high when either a) loss of input signal or b) the input signal level falls below apredetermined amplitude as set by R LV on pin 2. There will be several horizontal lines delay before the output isinitiated.11Burst/BackPorch OutputThe start of back porch output is triggered on the trailing edge of normal H sync, and on the rising edge of serrationpulses in the vertical interval. The pulse is timed out internally to produce a one-shot output. The pulse width is afunction of R SET . This output can be used for d.c. restore functions where the back porch level is a known reference.12R SET The current through the resistor R SET determines the timing of the functions within the I.C. These functions includethe sampling of the sync pulse 50% point, back porch output and the 2H eliminator. For faster scan rates, the resistorneeds to be reduced inversely. For NTSC 15.7kHz scan rate R SET is 681k 1%. R SET must be a 1% resistor.13Odd/EvenOutputOdd-even output is low for even field and high for odd field. The operation of this circuit has been improved forrejecting spurious noise pulses such as those present in VCR signals.14V DD 5VThe internal circuits are designed to have a high immunity to supply variations, although as with most I.C.s a 0.1µFdecoupling capacitor is advisable.15HorizontalSync OutputThis output produces only true H pulses of nominal width 5µs. The leading edge is triggered from the leading edgeof the input H sync, with the same prop. delay as the composite sync. The half line pulses present in the input signalduring vertical blanking are eliminated with an internal 2H eliminator circuit.16AnalogGroundThis is the ground return for the signal paths in the chips, R SET , R F and R LV . EL4583   4  FN7173.2May 5, 2006 Typical Performance Curves  R SET vsHorizontal FrequencyBack Porch ClampOn Time vs R SET Vertical Default DelayTime vs R SET Filter 3dB B W vs R F Level Out (Pin 9) vsSync. Tip AmplitudeMinimum Signal Detectvs R LV Filter Attenuation vs R F @f = 3.58MHz Note 1: For R LV < 1000k Ω , no signal detect output (pin 10) will default high atminimum signal sensitivity specification, or at complete loss of signal. EL4583 
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