Advances in Verification - Workshop at BMS College of Engineering

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1. Advances inVerification Methodologies Workshop at BMS college – June 2016 As part ofTEQIP 6/17/2016www.verificationexcellence.in 1 2. Verification with System…
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  • 1. Advances inVerification Methodologies Workshop at BMS college – June 2016 As part ofTEQIP 6/17/2016www.verificationexcellence.in 1
  • 2. Verification with System Verilog Ramdas M ExperiencedVerification Engineer, Applied Micro 17+ years experience, Author, OnlineTeacher, Blogger 6/17/2016www.verificationexcellence.in 2
  • 3. Introduction - Instructor ▪ ExperiencedVerification Engineer with 17 years of experience ▪ Applied Micro, Intel, IBM, C-DOT ▪ OnlineTeacher ▪ www.verificationexcellence.in ▪ FREE online courses on SystemVerilog, Assertions, Coverage, UVM ▪ Author ▪ Cracking Digital VLSIVerification Interviews: Interview Success ▪ Quora Blogger ▪ 200+ answers and 5 blogs, Most viewed writer inVLSI topics 6/17/2016www.verificationexcellence.in 3
  • 4. Agenda – Day 1 ▪ Day 1 - Morning ( 9 - 11) ▪ Introduction to SV - 10 mins ▪ Building blocks - 30 mins ▪ Language constructs -50 mins ▪ Exercise/Quiz/Q&A - 30 mins 6/17/2016www.verificationexcellence.in 4 ▪ Day 1 - Morning ( 11.15 - 1) ▪ Threads and Inter process communication ▪ Exercises/Quiz/Q& A ▪ Day 1 – Noon (2-4) ▪ SystemVerilog Classes ▪ Exercises/Quiz/Q& A
  • 5. Agenda – Day 2 ▪ Day 2 - Morning ( 9 - 11) ▪ Interfaces/Virtual Interfaces ▪ Randomization and Constraints ▪ Exercise/Quiz/Q&A 6/17/2016www.verificationexcellence.in 5 ▪ Day 2 -Noon ( 2-4) ▪ Lab Exercises
  • 6. Introduction to SystemVerilog Ramdas M 6/17/2016www.verificationexcellence.in 6
  • 7. What is SystemVerilog ▪ SystemVerilog is a combined hardware description language and hardware verification language ▪ SystemVerilog is an extensive set of enhancements to IEEE 1364Verilog-2001 standards ▪ It has features inherited fromVerilog HDL,VHDL,C,C++ 6/17/2016 www.verificationexcellence.in 7
  • 8. History and evolution of SV ▪ Verilog (IEEE standard 1364) ▪ Began in 1983 as a proprietary language ▪ Opened to the public in 1992 ▪ Became an IEEE standard in 1995 (updated in 2001 and 2005) ▪ Between 1983 and 2005 design sizes increased dramatically! ▪ SystemVerilog (IEEE standard 1800) ▪ Originally intended to be the 2005 update toVerilog ▪ Contains hundreds of enhancements and extensions toVerilog ▪ Published in 2005 as a separate document ▪ Officially supersededVerilog in 2009 ▪ Updated with more features in 2012 (IEEE 1800 2012 standard) 6/17/2016 www.verificationexcellence.in 8
  • 9. SystemVerilog – UserView ▪ SVD -SystemVerilog for Design ▪ Features supporting Design ▪ SVTB – SystemVerilog forTest benches ▪ Test bench specific Features ▪ SVA – SystemVerilogAssertions ▪ Features for temporal and concurrent assertions ▪ SVDPI – SV Direct Programming Interface ▪ For better C/C++ integration ▪ SVAPI – SV Application Programming Interface ▪ For better Coverage/Assertion integration 6/17/2016 www.verificationexcellence.in 9
  • 10. Verilog to SystemVerilog 6/17/2016www.verificationexcellence.in 10
  • 11. What isVerification ? ▪ Process of demonstrating functional correctness of a design. 6/17/2016 Verification with System Verilog 11
  • 12. SystemVerilog forVerification ▪ Where do we really use SystemVerilog Language inVerification ? ▪ Building Test bench components ▪ Stimulus generators, drivers ▪ Monitors, Checkers,Assertions ▪ Coverage ▪ Reference Models ▪ Test cases 6/17/2016www.verificationexcellence.in 12
  • 13. A VerificationTest bench 6/17/2016www.verificationexcellence.in 13
  • 14. Basic Building Blocks Srividhya TP 6/17/2016www.verificationexcellence.in 14
  • 15. Agenda ▪ What is coding for Design /Validation ▪ Delta overVerilog ▪ What should u Know in SystemVerilog ▪ UVM/System C 6/17/2016www.verificationexcellence.in 15
  • 16. SystemVerilog Enhancements ▪ Goal ▪ Model More functionality in fewer lines of code ▪ Reduce redundancy ▪ Reduce risk of coding errors 6/17/2016www.verificationexcellence.in 16
  • 17. How do u handle any HDL/Language ▪ U google  ▪ Design :Synthesizability ▪ What constructs are synthesizable ▪ What construct converts to what real logic? ▪ What are the diff optimized ways of coding? ▪ Coding for Performance, Power ▪ Macros that optimize place and route ▪ Latency, Different frequencies- FIFO Design, Standard library components ▪ Coding for FPGAs, Silicon debug ▪ Documentation; Specification ▪ Project independence 6/17/2016www.verificationexcellence.in 17
  • 18. Verification Mindset ▪ What is architecting forTestbench? Find Bugs known and unknown? ▪ How? ▪ Formal/ assertions ▪ Coverage ▪ How to eliminate Human dependency over generations ▪ What is a right construct? ▪ Simulation time.. ▪ Hierarchy porting ▪ UVM – refer slide 9 ▪ Error Scenarios ▪ Conferences 6/17/2016www.verificationexcellence.in 18
  • 19. Common mistakes - Design ▪ Coding? Instead ofArchitecting -- Clarity ▪ IP based approach? ▪ Assumptions not coded? ▪ Latency unknown ▪ Scaleability 6/17/2016www.verificationexcellence.in 19
  • 20. Common Mistakes -Verification ▪ Out of the Box thinking ▪ Architecting? ▪ Thinking Beyond the Spec ▪ Hard coding ▪ Scope for scalabilityTest /Testbench ▪ Human dependency ▪ EnhancingTB for feature is recoding/patching? ▪ Auto code generation ▪ TB randomness 6/17/2016www.verificationexcellence.in 20
  • 21. Design/Verification Building blocks ▪ Modules ▪ Interfaces ▪ Subroutines (Tasks, Functions) ▪ Packages ▪ Configurations ▪ Hierarchy 6/17/2016www.verificationexcellence.in 21
  • 22. Modules ▪ Basic building block for design/verification ▪ Ports with declarations (input, output ) ▪ Data declarations – nets, variables, structures ▪ Constants, user defined types ▪ Class definitions ▪ Import from packages ▪ Sub routine definition ▪ Instantiation of other modules, interfaces, ▪ Instantiation of class objects ▪ Continuous assignments 6/17/2016www.verificationexcellence.in 22
  • 23. Module example 6/17/2016www.verificationexcellence.in 23
  • 24. Module Instance and Port connections ▪ InVerilog, port connections must be named ▪ Very verbose and redundant info ▪ SV adds .name and .* shortcuts ▪ .name connects a port to a net of same name ▪ .* automatically connects all ports and nets with same name 6/17/2016www.verificationexcellence.in 24
  • 25. Interfaces ▪ A named bundle of nets or variables ▪ Encapsulates communication between blocks ▪ Connectivity - Port list and signals ▪ Functionality – Functions and tasks ▪ An instantiation of interface can be used to connect between multiple modules. ▪ A single name can replace a list of port 6/17/2016www.verificationexcellence.in 25
  • 26. Interface example ▪ How do we abstract signal between two design blocks like below? 6/17/2016www.verificationexcellence.in 26
  • 27. Interface Example ▪ Advantages ▪ Simplifies complex bus definitions and interconnections ▪ Ensures consistency through out design and verification blocks 6/17/2016www.verificationexcellence.in 27
  • 28. Interface - Another Example 6/17/2016www.verificationexcellence.in 28
  • 29. Interface Example 6/17/2016www.verificationexcellence.in 29
  • 30. Tasks and Functions - Usage ▪ Tasks ▪ Tasks can enable other tasks and functions ▪ Tasks may execute in non-zero simulation time. ▪ Tasks may have zero or more arguments of type input, output and inout. 6/17/2016www.verificationexcellence.in 30
  • 31. Synthesizable Variable types ▪ New useful synthesizable types ▪ logic - 4 state variable, user defined size (replaces reg) ▪ reg doesn’t always infer register ▪ Use of logic makes less confusion s in code ▪ enum – variable with specified set of legal values ▪ int - 32 bit 2 state variable ( can replace integer in for loops) ▪ Avoid using 2 state variables in synthesizable code 6/17/2016www.verificationexcellence.in 31
  • 32. Simplified port type rules ▪ Traditional verilog has strict and confusing port type rules ▪ Inputs must be declared wire ▪ Outputs must be ▪ reg if driven from procedural statement ▪ wire if driven by continuous statement ▪ wire if connected to module instances ▪ SystemVerilog makes it easy ▪ Declare all as logic 6/17/2016www.verificationexcellence.in 32
  • 33. Tasks and Functions - Usage ▪ Functions ▪ Function can enable other functions only. Task cannot be called from functions. ▪ Functions should execute in zero simulation time. ▪ Functions have only one return value but System Verilog also allows functions to have input, output or inout types. ▪ 6/17/2016www.verificationexcellence.in 33
  • 34. Tasks 6/17/2016www.verificationexcellence.in 34
  • 35. Functions 6/17/2016www.verificationexcellence.in 35
  • 36. Argument passing ▪ Pass by value ▪ Each argument is copied to the subroutine area 6/17/2016www.verificationexcellence.in 36 ▪ Pass by reference ▪ A reference to the original argument is passed instead of copying
  • 37. Packages ▪ Provides a declaration space that can be shared by building blocks ▪ Supports declaration of nets, variables, tasks, functions, classes, parameters etc ▪ Declarations can be imported to other building blocks by importing package 6/17/2016www.verificationexcellence.in 37
  • 38. Package: Example 6/17/2016www.verificationexcellence.in 38
  • 39. Package: Example 6/17/2016www.verificationexcellence.in 39
  • 40. Structure of a Design or Test bench code 6/17/2016www.verificationexcellence.in 40 Packages Module/Program always blocks/initial blocks/processes Parameters/defines, type defines, structs etc useful across files •Contains declarations •functions/tasks, data types, objects etc •Contains concurrent processes/blocks •module instance, continuous assign, always blocks etc •Contains sequential code •If then else, case etc -> control constructs •Repeat/for loops/do..while -> loops •Blocking/non-blocking assignments etc
  • 41. Language Constructs -DataTypes Ramdas M 6/17/2016www.verificationexcellence.in 41
  • 42. Data Types ▪ Nets ▪ Can be written by one or more continuous assignments ▪ No procedural assignment allowed ▪ Used to model physical connections (e.g. wires) ▪ Multiple drivers will result in a value based on net type 6/17/2016www.verificationexcellence.in 42
  • 43. Data Types ▪ Variables ▪ Can be written by one or more procedural assignments ▪ Or can be written by “one” continuous assignment ▪ Last write determines the value ▪ Normally declared as ▪ <data type> instance ▪ E.g. logic abc; ▪ e.g. int value; ▪ 2 state vs. 4 state variables ▪ Values = 0, 1, x and Z 6/17/2016www.verificationexcellence.in 43
  • 44. DataTypes ▪ 2 valued data types ▪ bit (1 bit) ▪ byte (8bits) ▪ shortint (16 bit) ▪ int (32 bits) ▪ 4 valued data types ▪ logic (1bit) ▪ integer (32 bit) ▪ Time (64 bit) 6/17/2016www.verificationexcellence.in 44
  • 45. Integer DataType 6/17/2016www.verificationexcellence.in 45
  • 46. Signed/UnsignedTypes ▪ byte, shortint, int, integer and longint defaults to signed ▪ Use unsigned to represent unsigned integer value ▪ time, bit, reg and logic defaults to unsigned ▪ Use signed to represent signed values ▪ Signedness can be explicitly defined as follows: 6/17/2016www.verificationexcellence.in 46
  • 47. Vectors ▪ Vectors are packed array of scalars ▪ Both MSB and LSB needs to be constant integer expressions ▪ Cannot be x (unknown) or z( high impedance) 6/17/2016www.verificationexcellence.in 47
  • 48. Strings 6/17/2016www.verificationexcellence.in 48 • String – ordered collection of characters • If not initialized defaults to empty string - “ “
  • 49. Strings - operators 6/17/2016www.verificationexcellence.in 49 Str1 == Str2 Equality Str1 != Str2 Inequality <, <=, >, >= Comparison {Str1, Str2, … Strn} Concatenation Str1[index] indexing – return 0 if out of range
  • 50. String Methods 6/17/2016www.verificationexcellence.in 50 • len • putc • getc • toupper • tolower • compare • icompare • substr • atoi, atohex, atoct, atobin • atoreal • itoa • hextoa • octtoa • bintoa • realtoa
  • 51. User defined types ▪ A typedef can be used to give a user defined name to an existing type 6/17/2016www.verificationexcellence.in 51
  • 52. EnumeratedTypes ▪ An enumerated type defines a set of named values. ▪ Defaults to “int” if data type declaration missing 6/17/2016www.verificationexcellence.in 52
  • 53. Defining new data types as enums ▪ A type name can be given to a enumerated type to create a new data type ▪ Ranges in elements ▪ Creates 5 elements sub0, sub1, sub2, sub3, sub4 and 3 elements jmp6, jmp7, jmp8 6/17/2016www.verificationexcellence.in 53
  • 54. Other data types ▪ void data type represents nonexistent data. Usually used for functions with no return values ▪ chandle data type represents storage for pointers passed using DPI ▪ class - A variable that can hold handle to a class object ▪ event – Provides a way of synchronization of two ore more concurrently active process ▪ Constant data types - parameters (evaluated elaboration time) and const (set during simulation) 6/17/2016www.verificationexcellence.in 54
  • 55. Other data types ▪ Aggregate Data types (Will explain in later section) ▪ Structures ▪ Unions ▪ Arrays ▪ Dynamic , Associative arrays ▪ Queues 6/17/2016www.verificationexcellence.in 55
  • 56. Operators and Expressions Ramdas 6/17/2016www.verificationexcellence.in 56
  • 57. Operators 6/17/2016www.verificationexcellence.in 57
  • 58. Operators 6/17/2016www.verificationexcellence.in 58
  • 59. Operators 6/17/2016www.verificationexcellence.in 59
  • 60. Operators ▪ Similar to other languages ▪ For more specifics refer to LRM Chapter 11 ▪ As this needs to be used as a reference 6/17/2016www.verificationexcellence.in 60
  • 61. Loops and Flow control Ramdas 6/17/2016www.verificationexcellence.in 61
  • 62. Loops and Flow Control ▪ If-else-if ▪ case/casex/casez ▪ forever ▪ repeat ▪ while ▪ do..while ▪ foreach 6/17/2016www.verificationexcellence.in 62
  • 63. Examples - Loops 6/17/2016www.verificationexcellence.in 63 for (int i; i < arr.size(); j+=2, i++) begin arr[i] += 200; arr[i]--; end 1)x = 0; while (x) begin $display(“%d”, x); x--; end 2) do begin $display(“%d”, x); x--; end while (x);
  • 64. forever ▪ Continuous execution, without end ▪ Used with timing controls ▪ Usually last statement in some block initial : clock_drive begin clk = 1’b0; forever #10 clk = ~clk; end : clock_drive 6/17/2016www.verificationexcellence.in 64
  • 65. repeat ▪ Repeat a block ‘x’ times, no conditional test ▪ repeat (expr) statement ▪ Example x = 0; repeat (16) begin $display(“%d”, x++); end 6/17/2016www.verificationexcellence.in 65
  • 66. case/casez/casex ▪ case: ▪ 4-value exact matching. ▪ No don’t cares allowed 6/17/2016www.verificationexcellence.in 66
  • 67. case/casez/casex ▪ casez/casex: ▪ Allows don’t care to be specified ▪ Useful for priority decoders ▪ casez will handle z as don’t care ▪ casex will handle both z and x as don’t care ▪ Not so commonly used in verification/testbench 6/17/2016www.verificationexcellence.in 67
  • 68. Arrays 6/17/2016www.verificationexcellence.in 68
  • 69. Fixed Size Arrays Declaring fixed-size arrays ▪ int values[0:15]; // 16 ints [0]..[15] ▪ int styles[16]; // 16 ints [0]..[15] Multi Dimensional ▪ int memarray [0:7][0:3]; //Verbose declaration ▪ memarray[7][3] = 1; // Set last array element ▪ int testarray [8][4]; // Compact declaration 6/17/2016www.verificationexcellence.in 69
  • 70. Packed Arrays ▪ An array that represents a contiguous set of bits ▪ Can access subfields of array as elements ▪ Can be made of only single bit data types – bit, logic, reg or enumerated types ▪ E.g.: bit [7:0] data //packed array of 8 bits 6/17/2016www.verificationexcellence.in 70
  • 71. Unpacked Arrays ▪ Unpacked arrays need not be set as contiguous bits in memory ▪ real latency [7:0]; // unpacked array of real types ▪ Unpacked arrays can be made of any data types ▪ Class record_c; ▪ record_c table[7:0] // unpacked array of objects 6/17/2016www.verificationexcellence.in 71
  • 72. Packed and Unpacked Arrays 6/17/2016 www.verificationexcellence.in 72
  • 73. Dynamic Arrays ▪ An array whose size can be changed at run time ▪ Uninitialized size will be zero 6/17/2016www.verificationexcellence.in 73
  • 74. Dynamic Arrays 6/17/2016www.verificationexcellence.in 74
  • 75. Dynamic Array - Methods 6/17/2016www.verificationexcellence.in 75 function int size() Returns the current size of the array int addr[ ] = new[256]; int j = addr.size(); // j = 256 function void delete() Empties array contents and zero-sizes it int addr[ ] = new[256]; addr.delete(); Resizing <array> = new[<size>](<src_array>); dyn= new[j * 2](fix);
  • 76. ArrayAssignments 6/17/2016www.verificationexcellence.in 76
  • 77. Associative Arrays 6/17/2016www.verificationexcellence.in 77 • Associative arrays are used when the size of the array is not known or the data is sparse. • Syntax: data_type array_name [index_type];
  • 78. Associative Array Methods Function Use num() / size() Returns number of entries delete(<index>) Index for delete optional. When specified used to delete given index else whole array. exists (<index>) Returns 1 if element exists at index else 0 first (<index>), last (<index>) assigns to the given index variable the value of the first/last (smallest/largest) index in the associative array. It returns 0 if the array is empty, and 1 otherwise. next (<index>), prev (<index>) finds the entry whose index is greater/smaller than the given index. 6/17/2016www.verificationexcellence.in 78
  • 79. Example : Printing an associative array 6/17/2016www.verificationexcellence.in 79
  • 80. Queues ▪ A queue is a variable size, ordered collection of homogeneous elements ▪ Can grow or shrink in size ▪ Few examples 6/17/2016www.verificationexcellence.in 80
  • 81. Queue Operators ▪ Q[ a : b ] yields a queue with b - a + 1 elements. ▪ If a > b , resultant queue will be an empty queue ▪ If a = b, resultant queue will be a single element queue ▪ If either a or b are 4-state expressions containing X or Z values, it yields the empty queue {}. ▪ Q[ a : b ] where a < 0 is the same as Q[ 0 : b ]. ▪ Q[ a : b ] where b > $ is the same as Q[ a : $ ]. 6/17/2016www.verificationexcellence.in 81
  • 82. Queue Methods 6/17/2016www.verificationexcellence.in 82
  • 83. Queue Methods 6/17/2016www.verificationexcellence.in 83
  • 84. Queues - Examples item = q1[0]; // read leftmost ( first ) item from list item = q1[$]; // read rightmost ( last ) item from list n = q1.size; // determine number of items on q1 q1 = q1[1:$]; // delete leftmost ( first ) item of q1 q1 = q1[0:$-1]; // delete rightmost ( last ) item of q1 for (int i=0; i < q1.size; i++) // step through a list using integers begin … end q1 = { }; // clear the q1 list 6/17/2016www.verificationexcellence.in 84
  • 85. Array locator methods ▪ Methods that allow searching through an array including queues ▪ Returns a queue of matching entries 6/17/2016www.verificationexcellence.in 85
  • 86. Array locator methods 6/17/2016www.verificationexcellence.in 86
  • 87. Array locator - Examples 6/17/2016www.verificationexcellence.in 87
  • 88. Array Ordering Methods ▪ reverse() reverses the order of the elements in the array ▪ sort() sorts the array in ascending order ▪ rsort() sorts the array in descending order ▪ shuffle() randomizes the order of the elements in the array 6/17/2016www.verificationexcellence.in 88
  • 89. Array Ordering Methods - Examples 6/17/2016www.verificationexcellence.in 89
  • 90. Exercises 6/17/2016www.verificationexcellence.in 90
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