Randomization and Constraints - Workshop at BMS College

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1. Advances inVerification Workshop Day 2 BMS College of Engineering, June 2016 6/17/2016www.verificationexcellence.in 1 2. Interfaces &Virtual Interfaces Deepti…
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  • 1. Advances inVerification Workshop Day 2 BMS College of Engineering, June 2016 6/17/2016www.verificationexcellence.in 1
  • 2. Interfaces &Virtual Interfaces Deepti Singh, Tech Lead,WaferSpace 6/17/2016www.verificationexcellence.in 2
  • 3. Port Interfaces -Verilog Description 6/17/2016www.verificationexcellence.in 3
  • 4. Interfaces in SystemVerilog 6/17/2016www.verificationexcellence.in 4
  • 5. Interfaces – Characteristics ▪ Brings abstraction-level enhancements to ports and internals ▪ Interface may contain any legal System Verilog code except module definitions and/or instances. ▪ tasks, functions, initial/always blocks, parameters, etc. ▪ Bus timing, pipelining, etc. may be captured in an interface rather than the connecting modules. ▪ Interfaces are defined once and used widely, so it simplifies design. ▪ Interfaces are synthesizable. 6/17/2016www.verificationexcellence.in 5
  • 6. ▪ Different users of interface need different views ▪ Master/Slave ▪ Monitor/driver ▪ Modport construct allows you to group signals and specify directions 6/17/2016www.verificationexcellence.in 6 ModPorts
  • 7. Mod port example 6/17/2016www.verificationexcellence.in 7
  • 8. Mod port example - usage 6/17/2016www.verificationexcellence.in 8
  • 9. Clocking Blocks ▪ Used to specify timing of synchronous signals with respect to clock ▪ Mainly used in test benches and inside interfaces ▪ It ensures that all signals are driven or sampled with same clock delays ▪ Interfaces can contain multiple clocking blocks (1 per clock) 6/17/2016www.verificationexcellence.in 9
  • 10. Clocking block syntax 6/17/2016www.verificationexcellence.in 10
  • 11. Clocking block -example 6/17/2016www.verificationexcellence.in 11
  • 12. Input and output skews ▪ Input and output signals are sampled at a clocking event. ▪ For an input skew, the signal is sampled at skew units before the clock event. ▪ For an output or inout, the signal is driven simulation time units after the corresponding clock. 6/17/2016www.verificationexcellence.in 12
  • 13. ▪ A skew value is a constant expression and can be specified by a parameter. ▪ If a number is used for the time then skew is interpreted based on timescale. ▪ An input skew of 1step indicates that the signal is sampled at the end of previous time step. 6/17/2016www.verificationexcellence.in 13 Input and output skews
  • 14. Clocking block example with skew and parameters 6/17/2016www.verificationexcellence.in 14
  • 15. Virtual Interfaces ▪ Classes cannot have modules or interfaces, need a specialized mechanism ▪ Why? ▪ Virtual interfaces provide a way to connect dynamic classes to static world of modules ▪ Virtual interfaces provide a mechanism for separating test programs/BFM models from the actual signals. 6/17/2016www.verificationexcellence.in 15
  • 16. Virtual Interface Example 6/17/2016 16 // interface definition interface Bus (input logic clk); bit req; bit grant; logic [7:0] addr; logic [7:0] data; endinterface: Bus // interface instance Bus infc_b (clk); // dut instance dut dut1 (infc_b, clk); // class instance BFM mybfm = new (infc_b); class BFM; virtual Bus bus; Xaction xaction; function new (virtual Bus b); // need to initialize virtual interface // in constructor bus = b; xaction = new; endfunction task req_bus(); @(posedge bus.clk); bus.req <= 1'b1; $display("Req = %b @ %0t", bus.req, $time); endtask: req_bus endclass: BFM www.verificationexcellence.in
  • 17. Random Constraints 6/17/2016www.verificationexcellence.in 17
  • 18. Simplest randomness ▪ $urandom system tasks ▪ $urandom() is SV, thread stable, deterministic ▪ $urandom returns unsigned 32-bit integers ▪ Procedural call can be inserted wherever needed 6/17/2016www.verificationexcellence.in 18
  • 19. Better Randomness ▪ Constraints are built onto the Class system ▪ Random variables use special modifier: ▪ rand –random variable ▪ randc –random cyclic variable ▪ Object is randomized by calling randomize( )method ▪ Automatically available for classes with random variables. ▪ User-definable methods ▪ pre_randomize() ▪ post_randomize() 6/17/2016www.verificationexcellence.in 19
  • 20. Constraints ▪ Set of Boolean algebraic expressions ▪ Example: ▪ constraint a_le_b { a <= b; } ▪ constraint c_eq_10 {c == 10;} ▪ constraint b_in_range { b >= 2 && b <= 8; } ▪ constraint all_gt_0 {a > 0; b > 0; c > 0;} 6/17/2016www.verificationexcellence.in 20
  • 21. Conflicting constraints ▪ What happens when you impose constraints that conflict in some way? ▪ Example: ▪ constraint x_gt_y { x > y; } ▪ constraint y_gt_z { y > z; } ▪ constraint z_gt_x { z > x; } ▪ … ▪ if ( x_inst.randomize() == 0 ) // Solver error ▪ begin ▪ … ▪ end 6/17/2016www.verificationexcellence.in 21
  • 22. Constraint operators ▪ Any Verilog boolean expression i.e. x < y+b-c*10>>20 ▪ Other constraint operations ▪ set membership within ▪ implication -> or if…else… ▪ iterative constraint foreach ▪ variable ordering solve … before ▪ functions func_x() 6/17/2016www.verificationexcellence.in 22
  • 23. Set membership constraint 6/17/2016www.verificationexcellence.in 23
  • 24. Implication constraint 6/17/2016www.verificationexcellence.in 24
  • 25. Implication constraint ▪ Uses one boolean to decide if another constraint must hold (trans_size == SMALL) -> (length < 10) (trans_size == MED) -> (length >= 10 && length <= 100) (trans_size == LARGE) -> (length > 100) 6/17/2016www.verificationexcellence.in 25
  • 26. Loop/array constraints ▪ Constrain every element of an array in some fashion, including reference to other elements of array constraint c1 { foreach ( A[i] ) A[i] inside {2, 4, 6, 8, 10}; } constraint c2 { foreach ( A[k] ) (k < A.size-1) -> A[k+1] > A[k]; } 6/17/2016www.verificationexcellence.in 26
  • 27. Distribution Constraints 6/17/2016www.verificationexcellence.in 27
  • 28. std::randomize() ▪ Procedural invocation of constraint solver ▪ Any variables can be the random variables ▪ “with” block for constraints ▪ Normal .randomize() cannot include variables outside scope of class 6/17/2016www.verificationexcellence.in 28
  • 29. Inline Constraints ▪ Specify inline constraints that are added to constraint set to solve trans.randomize() with { x < 100; z > buzz; }; 6/17/2016www.verificationexcellence.in 29
  • 30. Variable Ordering 6/17/2016www.verificationexcellence.in 30
  • 31. Enable/Disable rand/constraints ▪ rand_mode – method to toggle the “rand” attribute off on a class variable ▪ constraint_mode – method to toggle the application of a named constraint 6/17/2016www.verificationexcellence.in 31
  • 32. Layered Constraints ▪ Constraints Inherited via Class Extension ▪ Just like data and methods, constraints can be inherited or overridden 6/17/2016www.verificationexcellence.in 32 typedef enum{ low, high, other }AddrType; class MyBusextends Bus; rand AddrTypetype; constraint addr_rang { ( type == low ) =>addrin { [ 0 : 15] }; ( type == high ) =>addrin { [128 : 255] }; } endclass
  • 33. A Full Example 6/17/2016 33www.verificationexcellence.in
  • 34. A Full Example 6/17/2016 34www.verificationexcellence.in
  • 35. Functional Coverage 6/17/2016www.verificationexcellence.in 35
  • 36. Functional Coverage 6/17/2016www.verificationexcellence.in 36
  • 37. Functional Coverage 6/17/2016www.verificationexcellence.in 37
  • 38. Functional Coverage 6/17/2016www.verificationexcellence.in 38
  • 39. Functional Coverage 6/17/2016www.verificationexcellence.in 39
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